1. Field of the Invention
The present invention relates to a circuit for splitting a clock signal to produce two clock signals of differing phases that do not overlap one another.
2. Description of the Related Art
Digital circuits are known that are driven by two clock signals of differing phases that do not overlap. For example, a pipeline register may be driven by such clock signals to prevent race conditions as data propagates down the register.
FIG. 1 illustrates an exemplary circuit of a type known in the art that includes a register circuit 10 driven by two clock signals FCLK and FCLKN. FIG. 2 illustrates the timing of the clock signals. Two inverters 12 and 14 in series with one another produce a clock signal FCLK that is slightly delayed in time from a master clock signal CLK. A third inverter 16 produces a clock signal FCLKN that is the complement of FCLK and slightly delayed in time from CLK. The relative delay between clock signals FCLK and FCLKN at the inputs to register circuit 10 may vary due to tolerances of the components and propagation delays. Variation in the relative delay may be substantial when multiple register circuits 10 are driven by clock signals FCLK and FCLKN, due to loading and unequal transmission line lengths. As illustrated in FIG. 2, there is a time interval 18 during which both clock signal FCLK and clock signal FCLKN are changing state. This overlap may cause race conditions and other problems in register circuit 10.
It would be desirable to provide a circuit for producing two non-overlapping clock signals that is not detrimentally affected by component tolerances or propagation delays. The foregoing, together with other features and advantages of the present invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.